The present invention relates to a technology of actualizing a large-capacity memory module.
FIG. 1 illustrates an example of a configuration of a computer such as a server etc mounted with a byte-slice type memory controller.
CPUs and memory controllers 101 are connected to a system controller 100 that controls the device. At least one DIMM (Dual Inline Memory Module) is connected to each of the memory controllers 101, and a memory access is carried out in such a way that four pieces of memory controllers synchronize with each other (FIG. 1).
FIG. 2A-2C is a diagram of an outline of an architecture of the DIMM and shows an example of the 2-rank DIMM using a DDR2 (Double Data Rate 2) interface. The DIMM has eighteen pieces (18) of SDRAMs (Synchronous Dynamic Random Access Memories) at one rank, and therefore has totally thirty six (36) pieces of SDRAMs at two ranks as a whole of the DIMM.
In the DIMM having the plurality of ranks, the read and write from and to the respective ranks are selectively conducted by use of chip selection signals for the number of ranks (rank count). At the present, the DDR2 interface considered to be one of de facto standards has two chip selection signal lines and sixteen address signal lines A0-A15, wherein the rank count, in the case of adopting this interface, is “2” at the maximum, and a maximum readable/writable capacity using the sixteen address signal lines at 2 ranks is on the order of 16 GB.
Further, for instance, a technology disclosed in the following Patent document 1 is given as the prior art related to the invention of the present application.
[Patent document 1] Japanese Patent Application Laid-Open Publication No. 2003-7963